module TOP(
  input         clock,
  input         reset,
  input         io_pd_en,
  input  [7:0]  io_idx,
  input  [49:0] io_req_ptag,
  input  [49:0] io_meta_ptags_0,
  input  [49:0] io_meta_ptags_1,
  input  [49:0] io_meta_ptags_2,
  input  [49:0] io_meta_ptags_3,
  input  [49:0] io_meta_ptags_4,
  input  [49:0] io_meta_ptags_5,
  input  [49:0] io_meta_ptags_6,
  input  [49:0] io_meta_ptags_7,
  output [2:0]  io_predict_way,
  output        io_predict_hit,
  output        io_match_miss,
  output [63:0] io_total_cnt,
  output [63:0] io_hit_cnt_mul100,
  output        io_print
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  wp_clock; // @[TOP.scala 33:18]
  wire  wp_reset; // @[TOP.scala 33:18]
  wire  wp_io_predict_enable; // @[TOP.scala 33:18]
  wire [7:0] wp_io_idx; // @[TOP.scala 33:18]
  wire [2:0] wp_io_predict_way; // @[TOP.scala 33:18]
  wire  wp_io_predict_hit; // @[TOP.scala 33:18]
  wire [2:0] wp_io_correct_way; // @[TOP.scala 33:18]
  wire  wp_io_match_miss; // @[TOP.scala 33:18]
  reg [63:0] total_cnt; // @[TOP.scala 17:26]
  reg [63:0] hit_cnt; // @[TOP.scala 18:24]
  wire [63:0] _io_hit_cnt_mul100_T = hit_cnt * 7'h64; // @[TOP.scala 20:32]
  reg [63:0] print_cnt; // @[TOP.scala 22:26]
  wire [63:0] _print_cnt_T_1 = print_cnt + 64'h1; // @[TOP.scala 24:28]
  wire [3:0] _true_way_T_1 = io_meta_ptags_0 == io_req_ptag ? 4'h0 : 4'h8; // @[Mux.scala 80:57]
  wire [3:0] _true_way_T_3 = io_meta_ptags_1 == io_req_ptag ? 4'h1 : _true_way_T_1; // @[Mux.scala 80:57]
  wire [3:0] _true_way_T_5 = io_meta_ptags_2 == io_req_ptag ? 4'h2 : _true_way_T_3; // @[Mux.scala 80:57]
  wire [3:0] _true_way_T_7 = io_meta_ptags_3 == io_req_ptag ? 4'h3 : _true_way_T_5; // @[Mux.scala 80:57]
  wire [3:0] _true_way_T_9 = io_meta_ptags_4 == io_req_ptag ? 4'h4 : _true_way_T_7; // @[Mux.scala 80:57]
  wire [3:0] _true_way_T_11 = io_meta_ptags_5 == io_req_ptag ? 4'h5 : _true_way_T_9; // @[Mux.scala 80:57]
  wire [3:0] _true_way_T_13 = io_meta_ptags_6 == io_req_ptag ? 4'h6 : _true_way_T_11; // @[Mux.scala 80:57]
  wire [3:0] true_way = io_meta_ptags_7 == io_req_ptag ? 4'h7 : _true_way_T_13; // @[Mux.scala 80:57]
  reg  match_miss; // @[TOP.scala 40:27]
  wire [3:0] _GEN_5 = {{1'd0}, wp_io_predict_way}; // @[TOP.scala 41:38]
  reg  predict_hit; // @[TOP.scala 41:28]
  wire [63:0] _total_cnt_T_1 = total_cnt + 64'h1; // @[TOP.scala 44:28]
  reg  REG; // @[TOP.scala 46:30]
  wire [63:0] _hit_cnt_T_1 = hit_cnt + 64'h1; // @[TOP.scala 47:24]
  WayPredictor wp ( // @[TOP.scala 33:18]
    .clock(wp_clock),
    .reset(wp_reset),
    .io_predict_enable(wp_io_predict_enable),
    .io_idx(wp_io_idx),
    .io_predict_way(wp_io_predict_way),
    .io_predict_hit(wp_io_predict_hit),
    .io_correct_way(wp_io_correct_way),
    .io_match_miss(wp_io_match_miss)
  );
  assign io_predict_way = wp_io_predict_way; // @[TOP.scala 50:18]
  assign io_predict_hit = predict_hit; // @[TOP.scala 49:18]
  assign io_match_miss = match_miss; // @[TOP.scala 51:17]
  assign io_total_cnt = total_cnt; // @[TOP.scala 19:16]
  assign io_hit_cnt_mul100 = _io_hit_cnt_mul100_T[63:0]; // @[TOP.scala 20:21]
  assign io_print = print_cnt == 64'h64; // @[TOP.scala 26:18]
  assign wp_clock = clock;
  assign wp_reset = reset;
  assign wp_io_predict_enable = io_pd_en; // @[TOP.scala 54:24]
  assign wp_io_idx = io_idx; // @[TOP.scala 53:13]
  assign wp_io_predict_hit = predict_hit; // @[TOP.scala 55:21]
  assign wp_io_correct_way = true_way[2:0]; // @[TOP.scala 56:21]
  assign wp_io_match_miss = match_miss; // @[TOP.scala 57:20]
  always @(posedge clock) begin
    if (reset) begin // @[TOP.scala 17:26]
      total_cnt <= 64'h0; // @[TOP.scala 17:26]
    end else if (io_pd_en) begin // @[TOP.scala 43:17]
      total_cnt <= _total_cnt_T_1; // @[TOP.scala 44:15]
    end
    if (reset) begin // @[TOP.scala 18:24]
      hit_cnt <= 64'h0; // @[TOP.scala 18:24]
    end else if (predict_hit & REG) begin // @[TOP.scala 46:41]
      hit_cnt <= _hit_cnt_T_1; // @[TOP.scala 47:13]
    end
    if (reset) begin // @[TOP.scala 22:26]
      print_cnt <= 64'h0; // @[TOP.scala 22:26]
    end else if (print_cnt == 64'h64) begin // @[TOP.scala 26:28]
      print_cnt <= 64'h0; // @[TOP.scala 28:15]
    end else if (~reset) begin // @[TOP.scala 23:31]
      print_cnt <= _print_cnt_T_1; // @[TOP.scala 24:15]
    end
    match_miss <= true_way == 4'h8; // @[TOP.scala 40:37]
    predict_hit <= true_way == _GEN_5; // @[TOP.scala 41:38]
    REG <= io_pd_en; // @[TOP.scala 46:30]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  total_cnt = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  hit_cnt = _RAND_1[63:0];
  _RAND_2 = {2{`RANDOM}};
  print_cnt = _RAND_2[63:0];
  _RAND_3 = {1{`RANDOM}};
  match_miss = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  predict_hit = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  REG = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
